@techreport{lankamp13mgsim,
	Abstract = {MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.},
	Author = {Mike Lankamp and Raphael Poss and Qiang Yang and Jian Fu and Irfan Uddin and Chris R. Jesshope},


	Institution = {University of Amsterdam},
	Month = {February},
	Number = {arXiv:1302.1390v1 [cs.AR]},
	Read = {1},
	Title = {{MGSim}---Simulation tools for multi-core processor architectures},
	Url = {http://arxiv.org/abs/1302.1390},
	Urllocal = {pub/lankamp.13.mgsim.pdf},
	Year = {2013},
	}

{"_id":{"_str":"5342bd570e946d920a00350c"},"__v":1,"authorIDs":["54c2dea9b5fb1e5511000919","5dfafc26fa2bbbde01000122","5e35eb445cd57fde01000070","5e38ff13dc5b8ade01000077","5e64a5962551dede01000063","ZGRaLkjmxPcmJ739z","efnDKftzuGYiXXauW","pgjx6rQxQDmzHuwRK","sCob7zjTXbp95CmbP"],"author_short":["Lankamp, M.","Poss, R.","Yang, Q.","Fu, J.","Uddin, I.","Jesshope, C. R."],"bibbaseid":"lankamp-poss-yang-fu-uddin-jesshope-mgsimsimulationtoolsformulticoreprocessorarchitectures-2013","bibdata":{"bibtype":"techreport","type":"techreport","abstract":"MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.","author":[{"firstnames":["Mike"],"propositions":[],"lastnames":["Lankamp"],"suffixes":[]},{"firstnames":["Raphael"],"propositions":[],"lastnames":["Poss"],"suffixes":[]},{"firstnames":["Qiang"],"propositions":[],"lastnames":["Yang"],"suffixes":[]},{"firstnames":["Jian"],"propositions":[],"lastnames":["Fu"],"suffixes":[]},{"firstnames":["Irfan"],"propositions":[],"lastnames":["Uddin"],"suffixes":[]},{"firstnames":["Chris","R."],"propositions":[],"lastnames":["Jesshope"],"suffixes":[]}],"institution":"University of Amsterdam","month":"February","number":"arXiv:1302.1390v1 [cs.AR]","read":"1","title":"MGSim—Simulation tools for multi-core processor architectures","url":"http://arxiv.org/abs/1302.1390","urllocal":"pub/lankamp.13.mgsim.pdf","year":"2013","bibtex":"@techreport{lankamp13mgsim,\n\tAbstract = {MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.},\n\tAuthor = {Mike Lankamp and Raphael Poss and Qiang Yang and Jian Fu and Irfan Uddin and Chris R. Jesshope},\n\n\n\tInstitution = {University of Amsterdam},\n\tMonth = {February},\n\tNumber = {arXiv:1302.1390v1 [cs.AR]},\n\tRead = {1},\n\tTitle = {{MGSim}---Simulation tools for multi-core processor architectures},\n\tUrl = {http://arxiv.org/abs/1302.1390},\n\tUrllocal = {pub/lankamp.13.mgsim.pdf},\n\tYear = {2013},\n\t}\n\n","author_short":["Lankamp, M.","Poss, R.","Yang, Q.","Fu, J.","Uddin, I.","Jesshope, C. R."],"key":"lankamp13mgsim","id":"lankamp13mgsim","bibbaseid":"lankamp-poss-yang-fu-uddin-jesshope-mgsimsimulationtoolsformulticoreprocessorarchitectures-2013","role":"author","urls":{"Paper":"http://arxiv.org/abs/1302.1390","Local":"http://science.raphael.poss.name/pub/lankamp.13.mgsim.pdf"},"metadata":{"authorlinks":{"poss, r":"https://bibbase.org/show?bib=https%3A%2F%2Fscience.raphael.poss.name%2Fpub.bib"}}},"bibtype":"techreport","biburl":"http://science.raphael.poss.name/pub.bib","downloads":4,"keywords":[],"search_terms":["mgsim","simulation","tools","multi","core","processor","architectures","lankamp","poss","yang","fu","uddin","jesshope"],"title":"MGSim—Simulation tools for multi-core processor architectures","year":2013,"dataSources":["75cdFjzQkYc9cKbYS","ibJp9P4KitKPT3bh2","vwHwD5AQxBhRxMsmz","nMjrEFThibKqpZt4n","ob9Lo6tki9nBzzxK9"]}